Understanding PCIe Transaction Layer

1. Introduction

PCI Express (PCIe) is designed as a layered architecture to separate concerns such as packet generation, reliability, and physical transmission. Among these layers, the Transaction Layer plays a central role by translating software-level operations into structured packets that traverse the PCIe fabric.

This article presents a structured explanation of the Transaction Layer, focusing on its responsibilities, transaction types, and the detailed structure of Transaction Layer Packets (TLPs).

2. PCIe Layers

• Transaction Layer (TL): Generates Transaction Layer Packets (TLPs)
• Data Link Layer (DLL): Ensures reliable delivery of TLPs across a link
• Physical Layer (PHY): Handles electrical signaling and bit-level transmission

3. Role of Transaction Layer

The responsibilities listed below correspond to the Transaction Layer:

• Determines the destination using memory address or ID-based routing
• Converts read/write/configuration requests into Transaction Layer Packets (TLPs)

4. Types of PCIe Transactions

PCIe defines multiple transaction types:

Memory Transactions

• Memory Read
• Memory Write

Configuration Transactions

• Used during device enumeration
• Access configuration space

Message Transactions

• Interrupts (MSI/MSI-X)
• Power management
• Error signaling

Completion Transactions

• Responses to requests (e.g., returning data for a read request)

5. Transaction Layer Packet (TLP) Structure

A TLP is the fundamental unit of communication in PCIe.

+---------------------------------+
| TLP Header (3DW / 4DW)          |
+---------------------------------+
| Data Payload (optional)         |
+---------------------------------+
| Digest (optional)               |
+---------------------------------+

5.1 TLP Header

The TLP header defines the type, intent, and routing information of the packet.

DW0 — Format and Control:

31           24 23     20 19     16 15                0
+--------------+---------+---------+------------------+
| Fmt + Type   |  TC     | Attr    | Length           |
+--------------+---------+---------+------------------+

Key DW0 fields:

• Fmt (Format): 3 bits. Indicates header size (3DW or 4DW) and whether a data payload is present.

  • 000 = 3-DW header, no data (e.g., 32-bit Memory Read)
  • 001 = 4-DW header, no data (e.g., 64-bit Memory Read)
  • 010 = 3-DW header, with data (e.g., 32-bit Memory Write)
  • 011 = 4-DW header, with data (e.g., 64-bit Memory Write)

• Type: 5 bits. Combined with Fmt, defines the TLP type:

  • 00000 = Memory Read Request (MRd)
  • 00001 = Memory Read Request Locked (MRdLk)
  • 00000 with Fmt 010 = Memory Write (MWr)
  • 00100 = Configuration Read Type 0 (CfgRd0)
  • 00101 = Configuration Write Type 0 (CfgWr0)
  • 01010 = Completion (Cpl)
  • 01010 with Fmt 010 = Completion with Data (CplD)
  • 10000 = Message Request (Msg)

• TC (Traffic Class): 3 bits. Indicates priority (0–7). Most traffic uses TC0.

• Length: 10 bits. Specifies the number of DWORDs in the data payload (1–1024). A value of 0 represents 1024 DWORDs.

DW1 — Request Identification:

31              16 15        8 7         4 3         0
+------------------+----------+-----------+-----------+
| Requester ID     | Tag      | Last BE   | First BE  |
+------------------+----------+-----------+-----------+

Key DW1 fields:

• Requester ID: 16 bits. Identifies the source device using Bus/Device/Function (BDF).

Bus Number (8 bits) | Device Number (5 bits) | Function Number (3 bits)

• Tag: 8 bits. A unique identifier assigned by the requester.
  Used to match Completion TLPs with their corresponding requests.

• Last Byte Enable (Last BE): 4 bits. Indicates valid bytes in the last DWORD of the payload.
  Relevant for unaligned or partial transfers.

• First Byte Enable (First BE): 4 bits. Indicates valid bytes in the first DWORD of the payload.

Example (partial write):

Write 6 bytes starting at an offset within a DWORD:

DWORD N:
+----+----+----+----+
| B3 | B2 | B1 | B0 |
+----+----+----+----+
  ✔    ✔    ✔    ✘     → First BE = 1110

DWORD N+1:
+----+----+----+----+
| B3 | B2 | B1 | B0 |
+----+----+----+----+
  ✘    ✔    ✔    ✔     → Last BE = 0111

DW2/DW3 — Address:

• Contains the target address for Memory transactions
• DW2: Lower 32 bits of address
• DW3: Upper 32 bits (used only for 64-bit addressing)