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Why MLCC Lead Times Are Blowing Up in 2026 (And How to Design Around It)

If you've submitted a BOM for quoting recently and gotten a lead time that made you do a double take, you're not imagining things. Passive component sourcing in 2026 is tighter than it's been in a few years — and MLCCs are the e…

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If you've submitted a BOM for quoting recently and gotten a lead time that made you do a double take, you're not imagining things. Passive component sourcing in 2026 is tighter than it's been in a few years — and MLCCs are the epicenter.



I want to break down why this is happening, which component categories are actually at risk, and — more importantly — what you can do at the design stage to make your board less vulnerable to it. This isn't a "just wait it out" post; there are concrete layout and BOM decisions that meaningfully change your exposure.






Why now?



Three demand sources are converging on the same MLCC/inductor capacity that used to be dominated by consumer electronics:





  • AI server infrastructure — GPU power delivery networks alone can chew through hundreds of decoupling capacitors per board, and hyperscaler order volumes dwarf typical consumer runs.


  • EVs — automotive-grade passives (AEC-Q200, X8R/X7R) come from a narrower qualified supplier base, so even modest EV growth disproportionately tightens that segment.


  • Renewables/grid infrastructure — pulling on high-voltage inductors and power resistors.



On the supply side, new MLCC/ferrite production lines take 12–24 months to come online from the capital decision. Semiconductor fabs can reallocate capacity relatively fast; passive component fabs can't. That structural lag is the real reason lead times stretch out faster than they recover.






Which parts are actually at risk



Not everything is equally exposed:


















































Category Normal LT 2026 Tight-Market LT Exposure
Commercial MLCC (X7R, 0402/0603) 4–8 wks 8–16 wks Moderate–High
High-density MLCC (0201, high µF) 6–10 wks 16–26 wks High
Automotive MLCC (AEC-Q200, X8R) 10–14 wks 20–30+ wks Very High
C0G/NP0 (precision/timing) 4–8 wks 6–12 wks Low–Moderate
Power inductors (shielded, low DCR) 6–10 wks 12–20 wks Moderate–High
Chip resistors 2–6 wks 4–8 wks Low


Chip resistors are the least affected — manufacturing capacity is less concentrated and swapping vendors doesn't trigger a lot of requalification. High-density small-case MLCCs and automotive-grade parts are the ones to watch.






Design-stage mitigations that actually help



The cheapest fix is always the one that happens before layout is frozen:





  1. Specify parameter ranges, not exact part numbers. If the circuit tolerates it, give sourcing a capacitance/voltage/tolerance window instead of locking a single manufacturer's SKU.


  2. Don't over-spec. Using C0G where X7R would do, or ±1% where ±5% is fine, needlessly shrinks your supplier pool. Save tight specs for nets that actually need them (timing, precision sense).


  3. Prefer standard case sizes. A 0402 X7R in a common value has dramatically more second sources than a 0201 high-µF part pushed to the edge of the dielectric's spec.


  4. Dual-footprint critical passives where board area allows (e.g. pads that accept both 0402 and 0603) so a substitution doesn't require a respin.


  5. Flag single-source parts at design review, not after the BOM freezes — especially automotive-qualified or RF-specific components.






On the sourcing side



Submitting a complete BOM early lets a manufacturing partner flag long-lead items before they become a kitting-stage surprise. For low-volume/prototype runs, a small inventory buffer on known long-lead passives is cheap insurance against a handful of missing caps halting a whole build.






I wrote a longer version of this with a full lead-time reference table, a supply-resilient design checklist, and a section on how manufacturing partners can mitigate shortage exposure on their end (local component warehousing, incoming inspection for parts sourced under time pressure, etc.) — if you want the full breakdown: Passive Component Shortage 2026: MLCC Lead Times, Supply Chain Risk and Design Mitigation



Curious how others are handling this — are you dual-sourcing at design time, or mostly reacting once distributor stock runs out?

1. Sofort-Triage & Abwehrmaßnahmen

SOC Incident Playbook: Remote Code Execution (RCE) Defense
Syntax validiert (0 Fehler)
title: Detect Exploitation - Why MLCC Lead Times Are Blowing Up in 2026 (And How to Design Around It)
id: 59d5b6c0-b722-4c15-a251-795c201e1808
status: experimental
description: Automatisch generierte SIEM-Erkennungsregel basierend auf CTI Intelligence
references:
  - https://tsecurity.de/
author: iShareStuff CTI Automated Detection Engine
date: 2026-09-27
logsource:
  category: network_connection
  product: any
detection:
  selection:
      CommandLine|contains:
        - 'exploit'
  condition: selection
falsepositives:
  - Legitime administrative Zugriffe oder Penetrationstests
level: high
tags:
  - attack.initial_access
Syntax validiert (0 Fehler)
rule CTI_Threat_Indicator {
    meta:
        author = "iShareStuff CTI Automated Detection Engine"
        date = "2026-09-27"
        description = "YARA Signature for "
    strings:
        $str = "Why MLCC Lead Times Are Blowin" ascii wide
    condition:
        any of them
}
Syntax validiert (0 Fehler)
index=security sourcetype IN ("cisco:asa", "pan:traffic", "zeek_conn", "suricata", "WinEventLog:Security")
("Why MLCC Lead Times Are Blowing Up in 20")
| stats count earliest(_time) as first_seen latest(_time) as last_seen by src_ip, dest_ip, dest_host, signature
| eval first_seen=strftime(first_seen, "%Y-%m-%d %H:%M:%S"), last_seen=strftime(last_seen, "%Y-%m-%d %H:%M:%S")
| sort - count
Syntax validiert (0 Fehler)
message: "*Why MLCC Lead Times Are Blowing Up in 20*"
Syntax validiert (0 Fehler)
CommonSecurityLog
| where Message has "Why MLCC Lead Times Are Blowing Up in 20"
| summarize EventCount = count(), FirstSeen = min(TimeGenerated), LastSeen = max(TimeGenerated) by SourceIP, DestinationIP, DestinationPort, Activity
| extend DetectionRule = "iShareStuff-CTI-Compiled"
| sort by EventCount desc

2. Cyber Threat Intelligence & Forensik

🎯
MITRE ATT&CK Matrix Navigator 14 Taktiken
Reconnaissance
-
Resource Development
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Initial Access
Execution
Persistence
-
Privilege Escalation
Defense Evasion
Credential Access
-
Discovery
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Lateral Movement
-
Collection
-
Command and Control
Exfiltration
-
Impact
tsecurity.de Cognitive Threat RAG
Fokus-Vektor:

Analyse für identifizierte Bedrohung auf Basis von Live-CTI (ENISA EUVD): CVSS 0.0 · EPSS 0.0% · CISA KEV: nein. Handlungsableitung aus den verlinkten Hersteller-Quellen.

🛡️ Angriffsfläche & Exposure

Netzwerk/Remote-Zugriff ohne Vorauthentifizierung möglich.

⚡ Empfohlene Sofortmaßnahmen
  • 1. Perimeter-Inspektion: Relevante Portfreigaben und exponierte Endpunkte unverzüglich scannen.
  • 2. Patch-Applikation: Hersteller-Hotfix einspielen oder betroffene Daemons in isolierte DMZ-Segmente überführen.
  • 3. Telemetrie & EDR-Alerts: Prozessaufrufe und Child-Processes auf anomale Shell-Spawns überwachen.
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